library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;

entity serializer is
port (
	clk, rst: in std_logic;
	tx : out std_logic;
	data : in std_logic_vector(127 downto 0)
);
end serializer;

architecture Behavioral of serializer is

begin
process (clk, rst) 
begin
	if (rst = '1') then
		tx <= '0';
	elsif (rising_edge(clk)) then
		for i in 0 to 126 loop
			tx <= data(i) xor data(i+1);
		end loop;
	end if;
end process;

end Behavioral;
